1. Field of the Invention
The field of the invention is data processing, or, more specifically, multimodal memory controllers and methods for multimodal operation of a memory controller.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
As computing systems have evolved, at least two different computer memory bus architectures have emerged. On very low end computers, system designers integrate a memory controller directly into a system processor to access one or more channels of Dual In-line Memory Modules (‘DIMMs’) through a computer memory bus that implements a parallel, single-ended signaling protocol. Single-ended signaling is a method of transmitting electrical signals over a single signal line that is interpreted using a reference voltage. An advantage of single-ended signaling is the number of wires needed to transmit multiple signals simultaneously. If a bus needs to transmit n signals, then the bus needs to have at least n signal lines, likely more for voltage references or retiming signals. The main disadvantage of single-ended signaling is that the return currents for all the signals share the same wire and can sometimes cause interference, or crosstalk, between the signals. Such crosstalk typically limits the bandwidth of single-ended signaling systems. Examples of a parallel, single-ended signaling protocol may include Double Data Rate Two (‘DDR2’) or Double Data Rate Three (‘DDR3’). A computer bus that implements DDR2 uses 64 data lanes to transfer data at a maximum rate of 800 megabits per second and has a power supply rail voltage of 1.8 volts. A computer bus that implements DDR3 also uses 64 data lanes, but transfers data at a maximum rate of 1600 megabits per second and has a power supply voltage rail of 1.5 volts.
On higher end computer systems that require increased bandwidth, system designers configure a memory controller to access a memory buffer through a computer memory bus that implements a serial, differential signaling protocol. Differential signaling is a method of transmitting electrical signals over a pair of signal lines such that the sum of the voltages for the signals on the pair of signal lines remains constant. Differential signaling reduces the noise on a connection by rejecting common-mode interference. The pair of signal lines are routed in parallel, and sometimes twisted together, so that they will receive the same interference. One wire carries the signal, and the other wire carries the inverse of the signal. At the end of the connection, instead of reading a single signal, the receiving device reads the difference between the two signals. Because the receiver ignores the wires' voltages with respect to ground, small changes in ground potential between transmitter and receiver do not affect the receiver's ability to detect the signal. Furthermore, the system is immune to most types of electrical interference because any disturbance that alters the voltage level on one signal line will correspondently alter the voltage on the other signal line. Examples of a serial, differential signaling protocol may include a protocol according to the Fully Buffered DIMM One (‘FBDIMM1’) specification and the future Fully Buffered DIMM Two (‘FBDIMM2’) specification. The computer bus that implements the FBDIMM1 technology uses 24 data lanes per channel to transfer data at 4.8 gigabits per second and has a power supply rail of 1.5 or 1.2 volts. FBDIMM2 is specified to transfer data up to 9.6 gigabits per second with the same 24 lanes in the future. The memory buffer, in turn, accesses the DIMMs through one or more channels using lower bandwidth computer buses implementing a protocol such as, for example, DDR2 or DDR3.
The drawback to having these two computer memory bus architectures is that system designers must design and manufacture memory controllers with separate physical interfaces—one physical interface to drive a computer memory bus that implements a parallel, single-ended signaling protocol at one voltage, and another physical interface to drive a computer memory bus that implements a serial, differential signaling protocol at another voltage. As such, system designers must also design and manufacture separate sockets into which the memory controllers connect to a motherboard for each architecture. When the memory controller is integrated into the computer processor, separate computer processor must also be designed and manufactured for each architecture. Designing and manufacturing each of these separate components for the two architectures is time-consuming and costly. Readers will therefore appreciate that there is an ongoing need for innovation in the field of memory systems and, in particular, memory controllers.